Current Issue : October - December Volume : 2016 Issue Number : 4 Articles : 5 Articles
As safety and reliability critical components, lithium-ion batteries always require real-time\ndiagnosis and prognosis. This often involves a large amount of computation, which makes diagnosis\nand prognosis difficult to implement, especially in embedded or mobile applications. To address this\nissue, this paper proposes a run-time Reconfigurable Computing (RC) system on Field Programmable\nGate Array (FPGA) for Relevance Vector Machine (RVM) to realize real-time Remaining Useful Life\n(RUL) estimation. The system leverages state-of-the-art run-time dynamic partial reconfiguration\ntechnology and customized computing circuits to balance the hardware occupation and computing\nefficiency. Optimal hardware resource consumption is achieved by partitioning the RVM algorithm\naccording to a multi-objective optimization. Moreover, pipelined and parallel computation circuits\nfor kernel function and matrix inverse are proposed on FPGA to further accelerate the computation.\nExperimental results with two different battery data sets show that, without sacrificing the RUL\nprediction performance, the embedded RC platform significantly reduces the computation time\nand the requirement of hardware resources. This demonstrates that complex prognostic tasks can\nbe implemented and deployed on the proposed system, and it can be extended to the embedded\ncomputation of other machine learning algorithms....
As a modified-gravity proposal to handle the dark matter problem on galactic scales, Modified Newtonian Dynamics (MOND)\nhas shown a great success. However, the N-body MOND simulation is quite challenged by its computation complexity, which\nappeals to acceleration of the simulation calculation. In this paper, we present a highly integrated accelerating solution for N-\nbody MOND simulations. By using the FPGA-SoC, which integrates both FPGA and SoC (system on chip) in one chip, our\nsolution exhibits potentials for better performance, higher integration, and lower power consumption. To handle the calculation\nbottleneck of potential summation, on one hand, we develop a strategy to simplify the pipeline, in which the square calculation task\nis conducted by the DSP48E1 of Xilinx 7 series FPGAs, so as to reduce the logic resource utilization of each pipeline; on the other\nhand, advantages of particle-mesh scheme are taken to overcome the bottleneck on bandwidth. Our experiment results show that 2\nmore pipelines can be integrated in Zynq-7020 FPGA-SoC with the simplified pipeline, and the bandwidth requirement is reduced\nsignificantly. Furthermore, our accelerating solution has a full range of advantages over different processors. Compared with GPU,\nour work is about 10 times better in performance per watt and 50% better in performance per cost....
In order for a Mobile Device (MD) to support the Licensed Shared Access (LSA), the MD should be reconfigurable, meaning that\nthe configuration of a MD must be adaptively changed in accordance with the communication standard adopted in a given LSA\nsystem. Based on the standard architecture for reconfigurableMD defined inWorking Group (WG) 2 of the Technical Committee\n(TC) Reconfigurable Radio System (RRS) of the European Telecommunications Standards Institute (ETSI), this paper presents\na procedure to transfer control signals among the software entities of a reconfigurable MD required for implementing the LSA.\nThis paper also presents an implementation of a reconfigurable MD prototype that realizes the proposed procedure. The modem\nand Radio Frequency (RF) part of the prototype MD are implemented with the NVIDIA GeForce GTX Titan Graphic Processing\nUnit (GPU) and the Universal Software Radio Peripheral (USRP) N210, respectively. With a preset scenario that consists of five\ntime slots fromdifferent signal environments, we demonstrate superb performance of the reconfigurableMD in comparison to the\nconventional nonreconfigurable MD in terms of the data receiving rate available in the LSA band at 2.3ââ?¬â??2.4GHz....
This paper presents the design and implementation of a Stepper Motor using Nexys2 circuit board\nbased on a Xilinx Spartan 3E Field Programmable Gate Array (FPGA) device with VHDL code. The\nalgorithm implemented on FPGA allows a substantial decrease of the equivalent processing time\ndeveloped by different velocity controllers. The Stepper Speed control is achieved using VHDL\ncode, and the hardware digital circuit is designed for a programmable rotational stepper motor\nusing VHDL as a tool and FPGA as a target technology. The 50 MHZ provided by the starter kit is\ndivided to obtain the necessary delay time between the motor phases that ranges between 2 - 10\nm seconds. Though output selections, the direction of rotation of the stepper motor besides the\nmagnitude of the angle of movement and the rotation speed can be controlled. The major advantage\nof using reconfigurable hardware (FPGA) in implementing the Stepper Motor instead of a\ndiscrete digital component is that it makes modifications to the design easy and quick and also, the\ntotal design hence represents an embedded system (works without computer). The total programmable\nhardware design that controlled on the stepper motor movement, occupied an area\nthat did not exceed 12% of the chip resources....
Quasi-Passive Reconfigurable (QPAR) nodes have been proposed to provide flexible power/wavelength allocation in optical\naccess networks. QPAR only consumes power during reconfiguration, which is remotely transmitted from the central office, thus\nmaintaining the passive nature of the network. In this paper, a QPAR control circuit is designed, and a remotely powered and\nreconfigured 1 Ã?â?? 2 Ã?â?? 2 QPAR (i.e., one wavelength, two power levels, and two output ports) with a 0.1 F/5V supercapacitor (SC)\nremotely charged by a 1 Ã?â?? 8 photodiode array is experimentally demonstrated. The charged SC can power the QPAR for at least\n6 s with 24 consecutive reconfigurations (200ms each) or two reconfigurations within a maximum period of 40 hours, before the\nSC needs to be recharged. In addition, the demonstrated QPAR remote power scheme is compared with the previously proposed\nDirect Photovoltaic Power option both theoretically and experimentally. Results show that the SC based remote power mechanism\nis capable of driving a large number of reconfigurations simultaneously and it is better for large dimension QPARs....
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